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Honeywell 6000 series
The Honeywell 6000 series computers were a further development of General Electric's 600-series mainframes manufactured by Honeywell International, Inc. from 1970 to 1989. Honeywell acquired the line when it purchased GE's computer division in 1970 and continued to develop them under a variety of names for many years. In 1989, Honeywell sold its computer division to the French company Groupe Bull who continued to market compatible machines.
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The Honeywell 6000 series computers were a further development of General Electric's 600-series mainframes manufactured by Honeywell International, Inc. from 1970 to 1989. Honeywell acquired the line when it purchased GE's computer division in 1970 and continued to develop them under a variety of names for many years. In 1989, Honeywell sold its computer division to the French company Groupe Bull who continued to market compatible machines.
The Honeywell 6000 series computers were a further development (using integrated circuits) of General Electric's 600-series mainframes manufactured by Honeywell International, Inc. from 1970 to 1989. Honeywell acquired the line when it purchased GE's computer division in 1970 and continued to develop them under a variety of names for many years. In 1989, Honeywell sold its computer division to the French company Groupe Bull who continued to market compatible machines.
6000-series systems were said to be "memory oriented" — a system controller in each memory module arbitrated requests from other system components (processors, etc.). Memory modules contained 128 K words of 1.2 μs 36-bit words; a system could support one or two memory modules for a maximum of 256 K words (1 MB of 9-bit bytes). Each module provided two-way interleaved memory.
Devices called Input/Output Multiplexers (IOMs) served as intelligent I/O controllers for communication with most peripherals. The IOM supported two different types of peripheral channels: Common Peripheral Channels could handle data transfer rates up to 650,000 cps; Peripheral Subsystem Interface Channels allowed transfers up to 1.3 million cps.
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The high-end model was the 6080, with performance approximately 1 MIPS. Smaller models were the 6070, 6060, 6050, 6040, and 6030. In 1973, a low-end 6025 was introduced. The models with an even number as the next-to-last digit of the model number included an Enhanced Instruction Set feature (EIS), which added decimal arithmetic and storage-to-storage operations to the original word-oriented architecture. In 1973, Honeywell introduced the 6180, a 6000-series machine with addressing modifications to support the Multics operating system.
In 1974, Honeywell introduced several new computers under the name Series 60; the Level 66 and Level 68 members of the series were compatible with the 6000 series machines, and were slightly faster (to 1.2 MIPS) and offered larger MOS memories rather than core memories. The larger machines included a cache memory. The Level 66/20, Level 66/40, Level 66/60, and Level 66/80 were compatible with the 6040, 6060, and 6080; the Level 68/80 was compatible with the 6180, and supported Multics. Lower-end Level 66 and Level 68 processors were introduced in 1975; in the case of the Multics compatible 68/60, the key difference was the removal of the cache memory and limiting the configuration to a maximum of two processors.
In 1977, the line was again renamed to the 66/DPS (68/DPS for Multics compatible models). This was part of wide-scale repricing to remain compatible with the prices reductions that IBM had introduced to the market in early 1977. The newly introduced 68/DPS was available in at least five distinct configurations (Level1 through Level5).
During this period the top of the range was only comparable to the IBM System/370 Model 155/158 when it came to performance; this posed an issue for Honeywell when competing against the higher end of the System/370 family. This led to the development and the introduction of the Honeywell Model 66/85 in 1977. This system built with current-mode logic (CML) which promised to offer faster speeds in a more compact format. However Honeywell were unable to produce the CML chips in a cost-effective manner and subsequently withdrew the 66/85 from marketing in 1978.
In 1979, the family was renamed to DPS-8, again with a small performance improvement to 1.7 MIPS. GCOS 8 shipped as the native operating system with support for a new virtual memory hardware implementation (Virtual Unit - VU) that used a combination of Virtual Spaces, Paging, Segments and Domains. This was known as the "New System Architecture" (NSA) and was incompatible with the Multics model of virtual memory. As a result, modifications were required to ship the Multics compatible DPS-8/M which omitted the VU and instead implemented Multics Ring based securing model and the hybrid "Paged Segmentation" model of Multics virtual memory.
In 1982, Honeywell announced the new DPS-88 model which like the previous unsuccessful 66/85 was built using CML instead of the TTL as used in the previous DPS-8 generation. This required a switch from air cooling to using water cooling. The DPS-88 was offered in at two models based on the number of CPU's supported and memory supported: DPS-88/81 (64MB) and DPS-88/82 (128MB). Subsequently, Honeywell would sign a pact with NEC to import and sell NEC's S-1000 as the DPS-90.
The 6000 supported multiple processors and IOMs. Each processor and IOM had four ports for connection to memory; each memory module had eight ports for communication with other system components, with an interrupt cell for each port.
Memory protection and relocation was accomplished using a base and bounds register in the processor, the Base Address Register (BAR). The IOM was passed the contents of the BAR for each I/O request, allowing it to use virtual rather than physical addresses.
In the Multics-compatible systems there was an Appending Unit based on the unit of same name in the GE 645. This implemented the Multics model of virtual memory using "Paged Segments". These systems also had a hardware implementation of the Multics protection ring architecture, in contrast to the GE 645 which had emulated protection rings in software. This significantly improved the performance of ring passing events in Multics compared to on the GE 645.
From the DPS-8 generation onwards GCOS could use a competing Virtual Memory architecture that was not compatible with what Multics required from the hardware. That model divided the memory space into 512 Working spaces each of which were further divided into 1024 pages (in DPS-8 implementation) of 4096KB size. On top of this GCOS implemented Segments which could be grouped together in Domains (a Domain could have segments from multiple Working Spaces) which a process could access.
A variety of communications controllers could also be used with the system.
